TLK2201 Datasheet, PDF (3/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

block diagram
TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
PRBSEN
LOOPEN
REFCLK
MODESEL
ENABLE
TESTEN
RBC1
RBC0
SYNC/PASS
PRBS
Generator
10 Bit
TD(0–9) _Registers
2:1
MUX
Control
Logic
PRBS
Verification
Parallel to
Serial
Clock
Phase Generator
Interpolator
and
Clock Extraction
Clock
2:1
MUX
Clock
TXP
TXN
RD(0–9)
SYNCEN
RBCMODE
JTMS
JTRSTN
JTDI
TCK
Serial to Parallel
and
Comma Detect
JTAG
Control
Register
2:1
MUX
JTDO
Data
RXP
RXN
LOS
detailed description
data transmission
These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR
clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is
selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bit 0–4, and the falling edge of REFCLK clocks in bits
5–9. ( Bit 0 is the first bit transmitted).
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