TLC2543-EP Datasheet, PDF (9/25 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
CS
(see Note A)
I/O
CLOCK
1 2 3 4 5 6 7 8 11 12 ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ} 1
Access Cycle B
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _INPUT
A11
MSB
A10 A9
A8
A7
A6
A5
Previous Conversion Data
A4
A1
A0
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Hi-Z State
ÎÎÎÎÎÎÎÎ^BC17ÎÎÎι ÎÎÎÎ
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
5
6
7
8
11
12
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _INPUT
A11
MSB
A10 A9
A8
A7
A6
A5
Previous Conversion Data
A4
A1
B7
B6
B5
B4
B3
B2
B1
B0
A0
LSB
MSB
LSB
1
LowLevel _{ÎÎÎÎÎÎÎÎÎÎÎÎ}^BC17_{ÎÎÎÎ}¹ _{ÎÎÎÎ}
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval _Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
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