TLC2543-EP Datasheet, PDF (16/25 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
www.ti.com
Data Register, Bipolar Format
D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When
D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the
conversion result of an input voltage equal to V_ref– is a code of all zeros (000 . . . 0), the conversion result of an
input voltage equal to V_ref+ is a code of all ones (111 . . . 1), and the conversion result of (V_ref+ + V_ref–)/2 is a
code of a one followed by zeros (100 . . . 0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to V_ref– is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage
equal to V_ref+ is a code of a zero followed by all ones (011 . . . 1), and the conversion of (V_ref+ + V_ref–)/2 is a code
of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar
format in that the MSBs are always each other's complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
End of Conversion (EOC) Output
The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high.
During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains
high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch
occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in
the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting
the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the
falling edge of CS.
Data Format and Pad Bits
D3 and D2 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines
the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster 1-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.
When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT on
the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes
low and the serial output is forced to a setting of 0 until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
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