TLC2543-EP Datasheet, PDF (10/25 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
www.ti.com
CS
(see Note A)
I/O CLOCK
1
2
3
4
Access Cycle B
5
6
7
Sample Cycle B
8 ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ} 1
DATA OUT
ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATAINPUT
A7
A6
A5
A4
A3
A2
A1
A0
MSB
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
Hi-Z
B7
C7
MSB
LSB
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O CLOCK
1
2
3
4
5
6
7
8
Access Cycle B
Sample Cycle B
DATA OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DATA INPUT}
A7
A6
A5
A4
A3
A2
A1
A0
MSB
Previous Conversion Data
LSB
Low Level
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
1
ÎÎÎÎÎÎÎÎÎÎÎÎB7ÎÎÎÎÎÎÎÎ
C7
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
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