TLC2543-EP Datasheet, PDF (6/25 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
www.ti.com
Operating Characteristics
over recommended operating free-air temperature range, V_CC = V_ref+ = 4.5 V to 5.5 V, f_{(I/O CLOCK)} = 4.1 MHz
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾
MAX
E_L
Linearity error⁽²⁾
E_D
Differential linearity error
E_O
Offset error⁽³⁾
E_G
Gain error⁽³⁾
E_T
Total unadjusted error⁽⁵⁾
See Figure 2
See Figure 2
See Figure 2⁽⁴⁾
See Figure 2⁽⁴⁾
DATA INPUT = 1011
2048
±1
±1
±1.5
±1
±1.75
Self-test output code⁽⁶⁾ (see Table 3)
DATA INPUT = 1100
0
DATA INPUT = 1101
4095
t_(conv)
t_c
Conversion time
Total cycle time
(access, sample, and conversion)⁽⁷⁾
See Figure 9 through Figure 14
See Figure 9 through Figure 14
8
10
10 + total
I/O CLOCK
periods +
t_d(I/O-EOC)
t_acq
Channel acquisition time (sample)⁽⁷⁾
See Figure 9 through Figure 14
4
12
t_v
t_d(I/O-DATA)
t_d(I/O-EOC)
t_d(EOC-DATA)
t_PZH, t_PZL
t_PHZ, t_PLZ
t_r(EOC)
t_f(EOC)
t_r(bus)
t_f(bus)
t_d(I/O-CS)
Valid time,
DATA OUT remains valid after I/O
CLOCK↓
Delay time,
I/O CLOCK↓ to DATA OUT valid
Delay time,
last I/O CLOCK↓ to EOC↓
Delay time,
EOC↑ to DATA OUT (MSB/LSB)
Enable time,
CS↓ to DATA OUT (MSB/LSB driven)
Disable time,
CS↑ to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, last I/O CLOCK↓ to CS↓ to
abort conversion⁽⁸⁾
See Figure 6
See Figure 6
See Figure 7
See Figure 8
See Figure 3
See Figure 3
See Figure 8
See Figure 7
See Figure 6
See Figure 6
10
150
1.5
2.2
100
0.7
1.3
70
150
15
50
15
50
15
50
15
50
5
UNIT
LSB
LSB
LSB
LSB
LSB
µs
µs
I/O
CLOCK
periods
ns
ns
µs
ns
µs
ns
ns
ns
ns
ns
µs
(1) All typical values are at T_A = 25°C.
(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3) Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
(4) Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied
to REF– convert as all zeros (000000000000).
(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
(6) Both the input address and the output codes are expressed in positive logic.
(7) I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7)
(8) Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤5 µs of the
tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether the
conversion is aborted or the conversion results are valid.
6
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