TLC2543-EP Datasheet, PDF (11/25 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
5
6
7
8
Sample Cycle B
15
16 ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
1
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ INPUT
A15
MSB
A14 A13
A12 A11
A10
A9
Previous Conversion Data
A8
A1
A0
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Hi-Z State ÎÎÎÎÎÎÎÎBÎÎÎÎ15 ÎÎÎÎ
C7
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
5
6
7
8
15
16
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^INPUT
A15
MSB
A14 A13 A12 A11 A10 A9
Previous Conversion Data
A8
A1
A0
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
1
LowLevel ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎB15ÎÎÎÎÎÎÎÎ
C7
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t_(conv)
A/D Conversion
Interval
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time
has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
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11