DS90UB903QSQ Datasheet, PDF (9/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E – JUNE 2010 – REVISED APRIL 2013
Electrical Characteristics^(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
V_TH
Differential Threshold
High Voltage
(Figure 10)
V_TL
Differential Threshold
Low Voltage
-90
V_IN
Differential Input
Voltage Range
RIN+ - RIN-
180
I_IN
Input Current
V_IN = V_DD or 0V, V_DD = 1.89V
R_T
Differential Internal
Termination
Differential across RIN+ and RIN-
Resistance
-20
±1
80
100
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
I_DDT
Serializer (Tx)
VDDn Supply Current
(includes load
current)
R_T = 100Ω
WORST CASE pattern
(Figure 5)
R_T = 100Ω
VDDn = 1.89V
PCLK = 43 MHz
Default Registers
RANDOM PRBS-7 pattern
62
55
I_DDIOT
VDDIO = 1.89V
Serializer (Tx)
VDDIO Supply
Current (includes load
current)
R_T = 100Ω
WORST CASE pattern
(Figure 5)
PCLK = 43 MHz
Default Registers
VDDIO = 3.6V
PCLK = 43 MHz
2
7
Default Registers
I_DDTZ
V_DDn = 1.89V
370
I_DDIOTZ
Serializer (Tx) Supply PDB = 0V; All other
Current Power-down LVCMOS Inputs = 0V
V_DDIO = 1.89V
55
V_DDIO = 3.6V
65
I_DDR
Deserializer (Rx)
V_DDn = 1.89V, C_L = 8 pF
WORST CASE Pattern
PCLK = 43 MHz
SSCG[3:0] = ON
60
VDDn Supply Current _{(Figure 5)}
Default Registers
(includes load
current)
V_DDn = 1.89V, C_L = 8 pF
PCLK = 43 MHz
RANDOM PRBS-7 Pattern Default Registers
53
I_DDIOR
Deserializer (Rx)
VDDIO Supply
V_DDIO = 1.89V, C_L = 8 pF
WORST CASE Pattern
(Figure 5)
PCLK = 43 MHz
Default Registers
21
Current (includes load
current)
V_DDIO = 3.6V, C_L = 8 pF
WORST CASE Pattern
PCLK = 43 MHz
Default Registers
49
I_DDRZ
I_DDIORZ
Deserializer (Rx)
Supply Current
Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
V_DDn = 1.89V
V_DDIO = 1.89V
V_DDIO = 3.6V
42
8
350
Max
Units
+90
mV
mV
+20
µA
120
Ω
90
mA
5
mA
15
775
125
µA
135
96
mA
32
83
400
40
µA
800
Recommended Serializer Timing for PCLK⁽¹⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
Transmit Clock Period
Transmit Clock Input High
Time
Transmit Clock Input Low
Time
10 MHz – 43 MHz
23.3
0.4T
0.4T
T
0.5T
0.5T
t_CLKT
PCLK Input Transition Time
(Figure 11)
0.5
f_OSC
Internal oscillator clock
source
25
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
Max
100
0.6T
0.6T
3
Units
ns
ns
ns
ns
MHz
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