DS90UB903QSQ Datasheet, PDF (34/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
Figure 38 shows a typical connection of the DS90UB904Q Deserializer.
1.8V
C13 C11
FB1
C3
FB2
C4
FB3
C5
FB4
C15 C6
Serial
FPD-Link III
Interface
FB5
C16 C7
C1
C2
LVCMOS
Control
Interface
TP_A
TP_B
DS90UB904Q (DES)
VDDD
VDDIO1
C8
VDDR
VDDIO2
C9
VDDSSCG
VDDPLL
VDDCML
RIN+
RIN-
RES_PIN38
RES_PIN39
MODE
PDB
VDDIO3
C10
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
PCLK
VDDIO
FB6 C12 C14
LVCMOS
Parallel
Bus
VDDIO
RPU
RPU
I2C
Bus
Interface
SCL
FB7
SDA
FB8
C17
C18
Optional
NOTE:
Optional
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
RES_PIN46
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
GPI[0]
GPI[1]
GPI[2]
GPI[3]
LOCK
PASS
ID[X]
GPI
Control
Interface
1.8V
10 k:
RID
Figure 38. DS90UB904Q Typical Connection Diagram — Pin Control
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TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
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