DS90UB903QSQ Datasheet, PDF (26/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I²C bus through the bidirectional control
channel, slave clock stretching must be supported by the I²C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I²C slave pulls the SCL line low
prior to the 9th clock of every I²C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded.
Any remote access involves the clock stretching period following the transmitted byte, prior to completion of the
acknowledge bit. Since each byte transferred to the I²C slave must be acknowledged separately, the clock
stretching will be done for each byte sent by the host controller. For remote accesses, the “Response Delay”
shown is on the order of 12 µs (typical). See Application Note AN-2173 (SNLA131) for more details.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I²C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
1.8V
HOST
SCL
SDA
V_DDIO
RPU
RPU
10k
ID[x]
R_ID
SER
or
SCL _DES
SDA
To other
Devices
Figure 29. Bidirectional Control Bus Connection
Table 3. ID[x] Resistor Value – DS90UB903Q
Resistor RID Ω (±0.1%)
0, GND
2.0k
4.7k
8.2k
12.1k
39.0k
ID[x] Resistor Value - DS90UB903Q Ser
Address 7'b⁽¹⁾
7b' 101 1000 (h'58)
7b' 101 1001 (h'59)
7b' 101 1010 (h'5A)
7b' 101 1011 (h'5B)
7b' 101 1100 (h'5C)
7b' 101 1110 (h'5E)
Address 8'b 0 appended (WRITE)
8b' 1011 0000 (h'B0)
8b' 1011 0010 (h'B2)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
8b' 1011 1000 (h'B8)
8b' 1011 1100 (h'BC)
(1) Specification is ensured by design.
26
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB903Q DS90UB904Q