DS90UB903QSQ Datasheet, PDF (32/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have
settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to
ensure PDB arrives after all the VDD have stabilized.
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting. Note this function can be observed at the CMLOUTP/N test port
enabled via the control registers.
EMI REDUCTION
Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
Des Spread Spectrum Clocking
The DS90UB904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 35. Programmable PCLK Strobe Select
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