DS90UB903QSQ Datasheet, PDF (11/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E – JUNE 2010 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_DD
t_DDLT
t_RJIT
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Default Registers
Register 0x03h b[0]
(RRFB = 1) (Figure 17)
(Figure 15)⁽²⁾
(Figure 19,
Figure 21)⁽³⁾⁽⁴⁾
10 MHz–43 MHz
10 MHz–43 MHz
43 MHz
4.571T
+8
t_RCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF⁽¹⁾⁽⁵⁾
10 MHz
43 MHz
t_DPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF⁽¹⁾⁽⁶⁾
10 MHz
43 MHz
t_DCCJ
Deserializer Cycle-to-Cycle Clock PCLK
Jitter
SSCG[3:0] = OFF⁽¹⁾⁽⁷⁾
10 MHz
43 MHz
fdev
fmod
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 22)
20 MHz–43 MHz
20 MHz–43 MHz
Typ
Max
4.571T 4.571T
+ 12
+ 16
10
0.53
300
550
120
250
425
600
320
480
320
500
300
500
±0.5% to
±2.0%
9 kHz to
66 kHz
Units
ns
ms
UI
ps
ps
ps
%
kHz
(2) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) t_RJIT max (0.61UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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