CDCD5704 Datasheet, PDF (9/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
www.ti.com
SCAS823 – DECEMBER 2006
RECOMMENDED AC OPERATING CONDITIONS
MIN NOM MAX UNIT
t_CYCLE,IN REFCLK/REFCLKB input cycle time
t_CYC,TEST
t_J,IN
DC_IN
REFCLK/REFCLKB input cycle time for BYPASS
Input |cycle-to-cycle| jitter⁽¹⁾
Input duty cycle over 10,000 cycles⁽²⁾
t_r/t_f
Rise and fall time for REFCLK signal from 20% to 80% of input voltage V_IN
t_cr/t_cf
f_m,IN
P_{m tria}
P_{m n tria}
Difference between rise time and fall time of REFCLK signal from 20% to 80%
SSC frequency modulation repeat frequency⁽³⁾
Modulation index (= frequency deviation/center frequency) for triangle modulation⁽³⁾
Modulation index (= frequency deviation/center frequency) for non-triangle modulation⁽⁴⁾
t_SR
Input slew rate REFCLK/REFCLKB
SERIAL INTERFACE TIMING
f_SCLK
t_h(START)
t_w(SCLL)
t_w(SCLH)
t_su(START)
t_h(SDATA)
t_su(SDATA)
SCLK frequency⁽⁵⁾
START hold time⁽⁵⁾
SCLK low-pulse duration⁽⁵⁾
SCLK high-pulse duration⁽⁵⁾
START setup time⁽⁵⁾
SDATA hold time⁽⁵⁾
SDATA setup time⁽⁵⁾
t_r(SDATA)/
t_r(SM)
SDATA/SCLK input rise time⁽⁵⁾
t_f(SDATA)/
t_f(SM)
t_su(STOP)
SDATA/SCLK input fall time⁽⁵⁾
STOP setup time⁽⁵⁾
t_(BUS)
Bus free time
7
4
40%
175
30
1
0
4
4.7
4
4.7
300
250
4
4.7
11
40
185
60%
700
150
33
0.6%
0.5%
4
ns
ns
ps
ps
ps
kHz
V/ns
100 kHz
µs
µs
µs
µs
ps
ps
1000 ns
300 ns
µs
µs
(1) RefCLK jitter is measured at (V_IH(nom) – V_IL(nom))/2 and is the absolute value of the worst-case deviation.
(2) Measured at crossing points for differential clock input or at input threshold voltage V_TH for single-ended clock input.
(3) If input modulation is used; input modulation is allowed but not required.
(4) The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which
cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular
modulation is about 0.5%.
(5) See Figure 1 for the timing behavior of the serial interface.
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
OVERALL PARAMETER
I_DD
Supply current (= I_VDD + I_VDDP + I_VDDC)
V_PUC
Supply voltage threshold for power-up control
circuit
DC DEVICE CHARACTERISTICS
V_OX
V_COS
V_OL,ABS
V_ISET
Differential output crossing-point voltage⁽¹⁾
Output voltage swing (p-p, single-ended)⁽²⁾
Absolute output low voltage⁽³⁾
Reference voltage for swing control current
IREF ⁽⁴⁾
TEST CONDITIONS
At 300 MHz and 2.625 V
At 667 MHz and 2.625 V
Over complete supply voltage
range
Output load; see Figure 3.
V_DD = 2.375 V to 2.625 V, T = 0°C
to 70°C
MIN TYP MAX UNIT
70
85
mA
90
115
1.1
1.8
2.2 V
0.9
1
1.1 V
0.3 0.325 0.35 V
0.85
V
0.98
1 1.02 V
(1) V_OX is measured on external divider as shown in Figure 3.
(2) V_COS = (clock output high voltage – clock output low voltage), at the measurement points shown in Figure 3, excluding overshoot and
undershoot.
(3) V_OL,ABS is measured at the clock output of the package, instead of the measurement points of Figure 3.
(4) I_REF is equal to V_ISET/R_RC. Tolerance of R_RC must be ±1% or smaller.
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