CDCD5704 Datasheet, PDF (14/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
SCAS823 – DECEMBER 2006
APPLICATION INFORMATION
XDR Memory Subsystem (Source: Rambus)
XDR System Topology
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Termination
ASIC
PLL
´4
DRSL: 3.2 GHz
DQ BYTE [2N+1]
DQ BYTE [2N]
DQ BYTE [1]
DQ BYTE [0]
RSL: 800 MHz
RQ BUS [0:11]
XDR
DRAM n
·
·
·
XDR
DRAM 0
CFM 400 MHZ
System Clock
XDR
Clock
Generator
CDCD5704
CTM
400 MHZ
To Other Subsystems
M0054-01
14
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