CDCD5704 Datasheet, PDF (2/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
SCAS823 – DECEMBER 2006
www.ti.com
The bypass mode routes the input clock REFCLK to the differential output buffers, bypassing the PLL.
To ensure that the CDCD5704 clock generator always performs correctly, the device switches off the PLL and
the outputs are in the high-impedance state, once the clock input is below 10 MHz. If the supply voltage VDD is
less than V_PUC, all logic gates are reset, the PLL is powered down, and the outputs are in the high-impedance
state. Therefore, the device only starts its operation if these minimum requirements are met.
Because the CDCD5704 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to the
start of stabilization time.
The device operates from a single 2.5-V supply voltage. The CDCD5704 device is characterized for operation
from 0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
BYPASS
VDDP
VDDC
VDD
REFCLK
REFCLKB ^CLK0
PLL 1
300 MHz to 667 MHz
MUX
VDDP
VDDC
SDA
SCL
ID0
ID1
EN
VDD
Power
Down
Logic
Serial Interface
Control Logic
CLK0
CLk1
CLK2
CLK3
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
ISET
RSET
Current and Voltage
Reference
VSSP
VSSC
VSS
B0137-01
2
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