CDCD5704 Datasheet, PDF (7/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
www.ti.com
FUNCTIONAL DESCRIPTION OF THE LOGIC
SCAS823 – DECEMBER 2006
PLL Multiplication Factor Selection
Mult2
0
0 ⁽¹⁾
0
0
1
1
1
1
Mult1
0
0 ⁽¹⁾
1
1
0
0
1
1
Mult0
0
1 ⁽¹⁾
0
1
0
1
0
1
Multiplication
Factor
3
4 ⁽¹⁾
5
6
8
9/2
15/2
15/4
Output Frequency (MHz)
REFCLK = 100 MHz
REFCLK = 133 MHz
300
400
400
533
500
667
600
800 ⁽²⁾
800 ⁽²⁾
– ⁽²⁾
450
600
750 ⁽²⁾
– ⁽²⁾
375
500
(1) Default settings after power up
(2) Output at this frequency does not conform to all the ac device characteristics in the Device Characteristics table, or ouput frequency is
not supported.
Modes of Operation
EN
BYPASS Reg-Test RegA
RegB
RegC
RegD
CLK0
CLK1
CLK2
CLK3
L
X
X
X
X
X
X
HI-Z
HI-Z
HI-Z
HI-Z
H
X
1
X
X
X
X
RESERVED FOR VENDOR TEST
H
L
0
X
X
X
X
REFCLK REFCLK REFCLK REFCLK
H
H
0
0
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
H
H
0
1
0
0
0
PLL CLK
HI-Z
HI-Z
HI-Z
H
H
0
0
1
0
0
HI-Z
PLL CLK
HI-Z
HI-Z
H
H
0
1
1
0
0
PLL CLK PLL CLK
HI-Z
HI-Z
H
H
0
0
0
1
0
HI-Z
HI-Z
PLL CLK
HI-Z
H
H
0
1
0
1
0
PLL CLK
HI-Z
PLL CLK
HI-Z
H
H
0
0
1
1
0
HI-Z
PLL CLK PLL CLK
HI-Z
H
H
0
1
1
1
0
PLL CLK PLL CLK PLL CLK
HI-Z
H
H
0
0
0
0
1
HI-Z
HI-Z
HI-Z
PLL CLK
H
H
0
1
0
0
1
PLL CLK
HI-Z
HI-Z
PLL CLK
H
H
0
0
1
0
1
HI-Z
PLL CLK
HI-Z
PLL CLK
H
H
0
1
1
0
1
PLL CLK PLL CLK
HI-Z
PLL CLK
H
H
0
0
0
1
1
HI-Z
HI-Z
PLL CLK PLL CLK
H
H
0
1
0
1
1
PLL CLK
HI-Z
PLL CLK PLL CLK
H
H
0
0
1
1
1
HI-Z
PLL CLK PLL CLK PLL CLK
H
H
0 ⁽¹⁾
1 ⁽¹⁾
1 ⁽¹⁾
1 ⁽¹⁾
1 ⁽¹⁾
PLL CLK PLL CLK PLL CLK PLL CLK
(1) Default settings after power up
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