CDCD5704 Datasheet, PDF (8/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
SCAS823 – DECEMBER 2006
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_DD Supply voltage range
V_I Input voltage range ⁽²⁾
V_O Output voltage range ⁽²⁾
I_IK Input clamp current, (V_I < 0, V_I > V_DD)
I_O Continuous output current
R_θJA Thermal resistance, junction-to-ambient ⁽³⁾
R_θJC
R_θJB
T_J
T_stg
Thermal resistance, junction-to-case ⁽³⁾
Thermal resistance, junction-to-board ⁽³⁾
Maximum junction temperature
Storage temperature range
For SCL and SDA
For all other inputs
No airflow
Airflow 150 ft/min
Airflow 250 ft/min
Airflow 500 ft/min
No airflow
No airflow
VALUE
–0.3 to 2.8
–0.3 to 3.6
–0.3 to V_DD + 0.25
–0.5 to V_DD + 0.5
±20
±50
94.4
82.8
79.1
74
31.8
68.9
125
–65 to 150
UNIT
V
V
V
mA
mA
K/W
K/W
K/W
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S1P (high-k board).
RECOMMENDED DC OPERATING CONDITIONS
V_DDP
V_DDC
V_DD
T_A
V_IL,CLK
V_IX,CLK
V_IH,CLKD
∆V_IX,CLK
V_{IL SE}
V_{th SE}
V_{IH SE}
V_{IL L}
V_{IH L}
V_{IL SM}
V_{IH SM}
Supply voltage for PLL
Supply voltage for core
Supply voltage for clock buffers
Operating free-air temperature
Low-level input voltage, REFCLK/REFCLKB
Crossing-point voltage, input voltage threshold, REFCLK/REFCLKB
High-level input voltage, REFCLK/REFCLKB
Difference in crossing-point voltage
Low-level, single-ended input voltage, REFCLK
Single-ended input-voltage threshold, REFCLK ⁽¹⁾
High-level, single-ended input voltage, REFCLK
Low-level input voltage, ID0, ID1, EN, BYPASS
High-level input voltage, ID0, ID1, EN, BYPASS
Low-level input voltage, SCL, SDA ⁽²⁾
High-level input voltage, SCL, SDA ⁽²⁾
MIN
2.375
2.375
2.375
0
–0.15
0.2
0.6
–0.15
0.35
V_{th SE} + 0.3
–0.15
1.4
–0.15
1.4
NOM
2.5
2.5
2.5
MAX
2.625
2.625
2.625
70
0.15
0.55
0.95
0.15
V_{th SE} – 0.3
0.5 V_DD
2.625
0.8
2.625
0.8
3.465
UNIT
V
V
V
°C
V
V
V
V
V
V
V
V
V
V
V
(1) When using a single-ended clock input, V_th is supplied to the REFCLKB pin. Duty cycle of single-ended REFCLK input is measured at
V_th.
(2) This range of SCL and SDA input high voltage allows the CDCD5704 to co-exist with 3.3 V, 2.5 V, and 1.8 V devices on the same
serial-interface bus system.
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