CDCD5704 Datasheet, PDF (1/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

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Rambus™ XDR™ CLOCK GENERATOR
CDCD5704
SCAS823 – DECEMBER 2006
FEATURES
• High-Speed Clock Support: 300-MHz–667-MHz
Clock Source for XDR Memory Subsystems
and Redwood Logic Interface
• Quad (Open-Drain) Differential Output Drivers
• Spread-Spectrum Compatible Clock Input Can
Be Distributed to Minimize EMI
• Differential or Single-Ended Reference Clock
Input of 100 MHz or 133 MHz
• Serial Interface Features: Programmable
Frequency Multiplier, Select Any One to Four
Outputs and Mode of Operation
• Supports Frequency Multiplication Factors of:
×3, ×4, ×5, ×6, ×8, ×9/2, ×15/2, ×15/4
• All PLL Loop Filter Components Are
Integrated
• Low |Cycle-to-Cycle| of 1–6 Cycle Jitter:
– 40 ps: 300–635 MHz
– 30 ps: 636–667 MHz
• PLLs Are Powered Down if No Valid REF
Clock (<10 MHz) Is Detected or VDD Is Below
1.6 V
• Operates From Single 2.5-V Supply (±0.125 V)
• Packaged in TSSOP-28
• Commercial Temperature Range 0°C to 70°C
VDDP
VSSP
ISET
VSS
REFCLK
REFCLKB
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
BYPASS
PW PACKAGE
(TOP VIEW)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
VSS
CLK2
CLK2B
VSS
CLK3
CLK3B
VDD
P0043-01
APPLICATIONS
• XDR Memory Subsystem and Redwood Logic
Interface
DESCRIPTION
The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem
and Redwood logic interface using a reference clock input with or without spread-spectrum modulation.
Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an
off-the-shelf solution for a broad range of high-performance interface applications.
The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a
bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a
logical low at the input of the EN pin. An output is enabled when EN is high and a value of 1 is in its serial
interface register (RegA–RegD).
The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the
input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers
to drive the enabled clocks. Disabled outputs are set to high impedance.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Rambus, XDR are trademarks of Rambus Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated