CDCD5704 Datasheet, PDF (10/17 Pages) Texas Instruments – Rambus TM XDR TM CLOCK GENERATOR

CDCD5704
SCAS823 – DECEMBER 2006
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
I_OL/I_REF
I_OL,ABS
V_OL,SDA
PARAMETER
Ratio of output low current to reference current
Minimum current at V_OL,ABS(5)
SDA output low voltage
I_OL,SDA
SDA output low current
I_OZ
Output 3-state current
I_IR
REFCLK input current
I_IL
Logic input current
AC DEVICE CHARACTERISTICS
C_IR
Input capacitance, REFCLK,
REFCLKB ⁽⁶⁾
C_IL
Input capacitance logic pins⁽⁷⁾
t_CYCLE
Clock cycle time ⁽⁸⁾
t_jit(per)
|Cycle-to-cycle jitter| of 1–6 clock cycles
L₁
L₂₀
∆t_skew(o)
odc
SSB phase noise at 1 MHz
SSB phase noise at 20 MHz
Drift in t_skew(o) ⁽¹¹⁾
Output duty cycle
t_ODC,ERR
t_ERR,SSC
t_r/t_f
t_cr/t_cf
Z_OUT
|Cycle-to-cycle| duty-cycle error
PLL output phase error when tracking SSC
Output rise and fall time
Difference between output rise and fall times
Output dynamic impedance⁽¹²⁾
t_L
Power-up lock time
PLL lock time after (1) frequency change via
t_L(ω)
serial interface (programming of SCL and SDA
pins completed) or (2) EN and/or BYPASS
changed state
TEST CONDITIONS
V_OL,ABS = 0.85 V
V_DD = 2.375 V to 2.625 V,
I_OH = 4 mA
V_DD = 2.375 V to 2.625 V,
V_O = 0.8 V
CLK0 to CLK4
V_I = 0 V or V_DD
V_I = 0 V or V_DD
300 MHz to 667 MHz, possible
SSC is not taken into account
10,000 cycles, 300 MHz
to 635 MHz⁽⁹⁾
10,000 cycles, 636 MHz
to 667 MHz⁽⁹⁾
300-MHz–667-MHz output ⁽¹⁰⁾
300-MHz–667-MHz output⁽¹⁰⁾
V_DD = 2.375 V to 2.625 V,
T = 0 to 70°C
300 MHz to 635 MHz
636 MHz to 667 MHz
V_OUT = 20%–80%
V_OUT = 20%–80%, f_out = 300 MHz
to 667 MHz
V_OL = 0.9 V
Time from VDD, VDDP, VDDC
being applied and settled until
clock outputs are settled
Time from signals for selecting a
mode of operation (1) or (2)
applied and settled until clock
outputs are settled
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MIN TYP MAX UNIT
6.8
7
7.2
45
mA
0.4 V
6
mA
±50 µA
±5 µA
±10 µA
2
7 pF
2
10 pF
1.5
3.33 ns
45%
–100
100
750
–115
–150
50%
40
ps
30
–97 dBc/Hz
–128 dBc/Hz
15 ps
55%
40
ps
30
100 ps
300 ps
100 ps
Ω
3 ms
3 ms
(5) Minimum I_OL,ABS is measured at the clock output pins of the package, as shown in Figure 3.
(6) Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and V_AC < 100 mV
(7) Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and V_AC < 100 mV
(8) Maximum and minimum output clock cycle times are based on nominal output frequency of 300 MHz and 667 MHz, respectively. For
spread-spectrum-modulated differential or single-ended REFCLK, the output clock tracks the modulation of the input.
(9) Output short-term jitter specification is the absolute value of the worst-case deviation and is defined in the Jitter section.
(10) Device must not exceed the upper limit of L(f) for 1-MHz to 100-MHz offset as shown in the Phase Noise section.
(11) t_skew is the timing difference between any two of the four differential clocks and is measured at common-mode voltage. ∆t_skew is the
change in t_skew when the operating temperature and supply voltage change.
(12) Z_OUT is defined at the output pins directly. The value is determined as the ac small-signal impedance at low frequencies (< 100 kHz)
and when output is driving a high state.
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