CDC950 Datasheet, PDF (9/16 Pages) Texas Instruments – 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

CDC950
133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR
PC MOTHERBOARDS/SERVERS
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CLK33 (Type 5)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VDD = min to max,
VDD = 3.135 V,
VOL
Low-level output voltage
VDD = min to max,
VDD = 3.135 V,
VDD = 3.135 V,
IOH
High-level output current
VDD = 3.3 V,
VDD = 3.465 V,
VDD = 3.135 V,
IOL
Low-level output current
VDD = 3.3 V,
VDD = 3.465 V,
CO
Output capacitance
VDD = 3.3 V,
Zo
Output impedance
High state
Low state
VO = 0.5 VDD,
VO = 0.5 VDD,
† _{All typical values are measured at their respective nominal VDD values.}
IOH = –1 mA
IOH = −18 mA
IOL = 1 mA
IOL = 12 mA
VO = 1 V
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
VO = VDD or GND
VO/IOH
VO/IOL
MIN
VDD – 0.1
2.4
TYP†
0.15
−33
−53
−16
30
51
21
4.5
12
35
12
35
MAX
0.1
0.4
−33
38
7.5
55
55
UNIT
V
mA
pF
Ω
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(over)
V(under)
V(over)
V(under)
Overshoot†
Undershoot†
Overshoot†
Undershoot†
HCLK/HCLK 0.7-V
amplitude
Other clocks,
CL = worst case
GND − 0.7
VOH + 200
mV
VOL − 200
V
VDD + 0.7
tPZL
Output enable time
from low level
SEL100/133
All outputs
SEL100/133 ↑
Rref = 475 Ω
10
tPZH
tPHZ
Output enable time to
high level
Output disable time
from high level
SEL100/133
SEL100/133
All outputs
All outputs
SEL100/133 ↑
Rref = 475 Ω
SEL100/133 ↓
Rref = 475 Ω
10
ns
10
tPLZ
Output disable time
from low level
SEL100/133
All outputs
SEL100/133 ↓
Rref = 475 Ω
10
ts
Stabilization time‡
VDD
PWRDWN
All outputs After power up
All outputs From PWRDWN ↑
0.1 ms
0.25 ms
† _{These parameters are assured by design and lab characterization, not 100% production tested.}
‡ _{Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for}
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time since VDD achieves its nominal operating level (3.3 V) or PWRDWN transition from a low to a high level (2 V) until the output frequency is
stable and operating within specification.
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