CDC950 Datasheet, PDF (5/16 Pages) Texas Instruments – 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

CDC950
133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR
PC MOTHERBOARDS/SERVERS
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003
Function Tables (Continued)
Table 5. Host/HOST Output Buffer Specifications
INPUT
MultSel0 MultSel1
BOARD TARGET
TRACE/TERM Z
REFERENCE R,
IREF = VDD/(3 Rr)
OUTPUT CURRENT
IOH
VOH at Z
0
0
0
0
0
1
60 Ω
50 Ω
60 Ω
Rr = 475 1%,
Rr = 475 1%,
Rr = 475 1%,
I_REF = 2.32 mA
I_REF = 2.32 mA
I_REF = 2.32 mA
5 × IREF
5 × IREF
6 × IREF
0.71 V at 60 Ω
0.59 V at 50 Ω
0.85 V at 60 Ω
0
1
50 Ω
Rr = 475 1%,
I_REF = 2.32 mA
1
0
60 Ω
Rr = 475 1%,
I_REF = 2.32 mA
1
0
50 Ω
Rr = 475 1%,
I_REF = 2.32 mA
1
1
60 Ω
Rr = 475 1%,
I_REF = 2.32 mA
1
1
50 Ω
Rr = 475 1%,
I_REF = 2.32 mA
0
0
30 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
0
0
25 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
0
1
30 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
0
1
25 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
6 × IREF
4 × IREF
4 × IREF
7 × IREF
7 × IREF
5 × IREF
5 × IREF
6 × IREF
6 × IREF
0.71 V at 50 Ω
0.56 V at 60 Ω
0.47 V at 50 Ω
0.99 V at 60 Ω
0.82 V at 50 Ω
0.75 V at 30 Ω
0.62 V at 25 Ω
0.90 V at 30 Ω
0.75 V at 25 Ω
1
0
30 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
4 × IREF
0.60 V at 30 Ω
1
0
25 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
4 × IREF
0.5 V at 25 Ω
1
1
30 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
7 × IREF
1.05 V at 30 Ω
1
1
25 (dc equivalent) Rr = 221 1%,
I_REF = 5 mA
7 × IREF
0.84 V at 25 Ω
NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†
Supply voltage range, V_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.3 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD + 0.5 V
Voltage range applied to any output in the high-impedance or power-off state, V_O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD + 0.5 V
Current into any output in the low state, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × rated I_OL
Input clamp current, I_IK: (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V_I > V_DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK: (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
V_O > V_DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ_JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Maximum power dissipation at T_A = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 mW
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
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