CDC950 Datasheet, PDF (10/16 Pages) Texas Instruments – 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

CDC950
133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR
PC MOTHERBOARDS/SERVERS
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C (continued)
HCLK/HCLK (Type X1), C_L = 2 pF, R_ref = 475 Ω, 6 x R_ref
PARAMETER
TEST CONDITIONS
MIN TYP
HCLK clock period‡
Tjit(cc) Cycle-to-cycle jitter
f(HCLK) = 100 MHz
f(HCLK) = 133 MHz
f(HCLK) = 100 or 133 MHz
SSC off
SSC on
10
7.5
−80
−110
tdc
Duty cycle
f(HCLK) = 100 or 133 MHz,
Crossing point
45%
tsk(o) HCLK bus skew
f(HCLK) = 100 or 133 MHz,
Crossing point
tr
Rise time†
tf
Fall time†
0.7-V amplitude
VO = 0.14 V to 0.56 V
VO = 0.14 V to 0.56 V
v(cross) Cross point voltages†
0.7-V amplitude
f(HCLK) = 100 or 133-MHz
HCLK and HCLK
† _{These parameters are assured by design and lab characterization, not 100% production tested.}
‡ _{The average over any 1-µs period of time is greater than the minimum specified period.}
70
175
175
45%
VOH
CLK33 (Type 5), C_L = 30 pF, R_L = 500 Ω
PARAMETER
TEST CONDITIONS
PCI clock period†
f(HCLK) = 100 or 133 MHz
Tjit(cc) Cycle-to-cycle jitter
f(HCLK) = 100 or 133 MHz
t(dc)
Duty cycle
f(CLK33) = 33.3 MHz
tr
Rise time
VO = 0.4 V to 2.4 V
tf
Fall time
VO = 0.4 V to 2.4 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN
30
−150
45%
0.5
0.5
TYP
30.06
3V48 (Type 3), C_L = 20 pF, R_L = 500 Ω
PARAMETER
TEST CONDITIONS
MIN TYP
Tjit(cc)
tdc
tr
tf
3V48 clock period
Cycle-to-cycle jitter
Duty cycle
Rise time
Fall time
f(HCLK) = 100 or 133 MHz
f(HCLK) = 100 or 133 MHz
f(3V48) = 48 MHz
VO = 0.4 V to 2.4 V
VO = 0.4 V to 2.4 V
−300
45%
1
1
20.83
MAX
10.2
7.65
80
110
55%
700
700
55%
VOH
MAX
30.6
150
55%
2
2
MAX
300
55%
4
4
UNIT
ns
ps
ps
ps
V
UNIT
ns
ps
ns
UNIT
ns
ps
ns
REF (Type 3), C_L = 20 pF, R_L = 500 Ω
PARAMETER
TEST CONDITIONS
REF clock period
f(REF) = 14.318 MHz
Tjit(cc)
t(dc)
tr
tf
Cycle-to-cycle jitter
Duty cycle
Rise time
Fall time
f(HCLK) = 100 or 133 MHz
f(REF) = 14.318 MHz
VO = 0.4 V to 2.4 V
VO = 0.4 V to 2.4 V
MIN
−0.5
45%
1
1
TYP
69.84
MAX
0.5
55%
4
4
UNIT
ns
ns
10
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