CDC950 Datasheet, PDF (4/16 Pages) Texas Instruments – 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

CDC950
133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR
PC MOTHERBOARDS/SERVERS
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003
Function Tables
INPUTS
SEL100/133 SelA
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
SelB
0
1
0
1
0
1
0
1
Table 1. Select Functions
HCLK, HCLK
100 MHz
100 MHz
105 MHz
Hi-Z
133 MHz
127 MHz
133 MHz
TCLK/2
OUTPUTS
CLK33 3V48, 3V48
33 MHz
48 MHz
33 MHz
L, H
35 MHz
48 MHz
Hi-Z
Hi-Z
33 MHz
48 MHz
31.7 MHz
48 MHz
33 MHz
48 MHz
TCLK/8
TCLK/2
REFCLK
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
FUNCTION
Active 100 MHz
100 MHz mode; PLL48 powerdown
100 MHz mode 5% overclocking
All 3-state outputs
Active 133 MHz
133 MHz mode −5% underclocking
Test mode
Test mode (PLL bypass)
INPUT
PWRDWN
0
1
HCLK
2 × IREF
On
Table 2. Enable Functions
HCLK
Hi-Z
On
OUTPUTS
CLK33 3V48
L
L
On
On
3V48
H
On
REFCLK
L
On
Table 3. Output Buffer Specifications
BUFFER NAME
3V48, REFCLK
CLK33
HCLK/HCLK
VDD RANGE
(V)
3.135 − 3.465
3.135 − 3.465
3.135 − 3.465
IMPEDANCE
(Ω)
20−60
12−55
BUFFER TYPE
TYPE 3
TYPE 5
TYPE X1
Table 4. Spread Spectrum Functions
INPUT
SPREAD
0
1
OUTPUTS
Spread spectrum clocking active, −0.6% at HCLK/HCLK, CLK33
Spread spectrum clocking inactive
4
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265