CDC950 Datasheet, PDF (1/16 Pages) Texas Instruments – 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

CDC950
133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR
PC MOTHERBOARDS/SERVERS
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003
D Generates Clocks for Next Generation
Microprocessors
DGG PACKAGE
(TOP VIEW)
D Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
Theoretical EMI of 7 dB
D Power Management Control Terminals
D Low Output Skew and Jitter for Clock
Distribution
D Operates From a Single 3.3-V Supply
D Generates the Following Clocks:
− 8 Host (Diff Pairs, 100/133 MHz)
− 1 CLK33 (3.3 V, 33.3 MHz)
− 1 REFCLK (3.3 V, 14.318 MHz)
− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)
D Packaged in a 48-Pin TSSOP Package
CLK33 1
V_DD3.3V 2
3V48/SelA 3
3V48/SelB 4
GND 5
V_DD3.3V 6
HCLK(0) 7
HCLK(0) 8
GND 9
HCLK(1) 10
HCLK(1) 11
V_DD3.3V 12
HCLK(2) 13
HCLK(2) 14
GND 15
HCLK(3) 16
48 SEL100/133
47 GND
46 AV_DD3.3V
45 AGND
44 PWRDWN
43 V_DD3.3V
42 HCLK(4)
41 HCLK(4)
40 GND
39 HCLK(5)
38 HCLK(5)
37 V_DD3.3V
36 HCLK(6)
35 HCLK(6)
34 GND
33 HCLK(7)
description
The CDC950 is a differential clock synthesizer/
driver that generates HCLK/HCLK, CLK33, 3V48,
and REFCLK system clock signals to support a
HCLK(3) 17
V_DD3.3V ¹⁸
REFCLK ¹⁹
SPREAD ²⁰
GND ²¹
32 HCLK(7)
31 _VDD3.3V
30 _MultSel0
29 _MultSel1
28 _GND
computer system with next generation processors
XIN ²²
27 _AGND
and double data rate (DDR) memory subsystems.
XOUT ²³
26 _{I_REF}
All output frequencies are generated from a
V_DD3.3V ²⁴
25 _AVDD3.3V
14.318-MHz crystal input. A reference clock input
can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the
host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the
need for external components.
The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock
operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,
3V48/SelA, and 3V48/SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the
PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers
down completely with the HOST clock at 2 × I_REF, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are
in a low-level output state and 3V48B is in a high-level output state.
The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding
setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.
Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as following changes to the SEL inputs. With the
use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time
starts. The CDC950 is characterized for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001 − 2003, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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