AMC7812 Datasheet, PDF (9/92 Pages) Texas Instruments – 12-Bit ANALOG MONITORING AND CONTROL SOLUTION with Multichannel ADC, DACs, and Temperature Sensors

AMC7812
www.ti.com
SBAS513D – JANUARY 2011 – REVISED OCTOBER 2012
PIN DESCRIPTIONS
PIN (QFN / HTQFP)
NO.
NAME
DESCRIPTION
1
RESET
Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.
Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion
2
DAV
ends. In auto mode, a 1µs pulse (active low) appears on this pin when a conversion cycle finishes (see the
Primary ADC Operation and Registers sections for details). DAV stays high when deactivated.
3
CNVT
External conversion trigger, active low. The falling edge starts the sampling and conversion of the ADC.
4
SDI/SDA
Serial interface data. SDI for the serial peripheral interface (SPI) when the SPI/I2C pin is high. SDA for I²C
when the SPI/I2C pin is low.
5
SCLK/SCL
Serial clock input of the main serial interface. SPI clock when the SPI/I2C pin is high; I²C clock when the
SPI/I2C pin is low.
6
DGND
Digital ground
7
IOV_DD
Interface power supply
8
DV_DD
Digital power supply (+3V to +5V). Must be the same value as AV_DD.
9
CS/A0
Chip select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I²C when the SPI/I2C
pin is low.
10
SDO/A1
SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I²C when the SPI/I2C pin is low.
11
A2
Slave address selection A2 for I²C when the SPI/I2C pin is low.
12
SPI/I2C
Interface selection pin. Digital input. When this pin is tied to IOV_DD, the SPI is enabled and the I²C interface is
disabled. When this pin is tied to ground, the SPI is disabled and the I²C interface is enabled.
13
GPIO-0
14
GPIO-1
General-purpose digital input/output. This pin is a bidirectional open-drain, digital input/output, and requires an
15
GPIO-2
external pull-up resistor. See the General Purpose Input/Output Pins section for more details.
16
GPIO-3
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter
a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.
17
DAC-CLR-0 However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC
Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,
regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.
18
DAC5-OUT
19
DAC4-OUT Output of DAC channels 3, 4, and 5
20
DAC3-OUT
21
AGND4
Analog ground
22
AGND3
23
AV_CC2
Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, DAC5-OUT, must be
tied to AV_CC1
24
DAC2-OUT
25
DAC1-OUT Output of DAC channels 0, 1, and 2
26
DAC0-OUT
27
D2–/GPIO-6 Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pull-up required for output.
28
D2+/GPIO-7 Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pull-up required for output.
29
D1–/GPIO4 Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pull-up required for output.
30
D1+/GPIO-5 Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pull-up required for output.
31
ADC-REF-IN/CMP
External ADC reference input when external V_REF is used to drive ADC. Compensation capacitor connection
(connect 4.7µF capacitor between this pin and AGND) when Internal V_REF is used to drive ADC.
32
ADC-GND
ADC ground. Must be connected to AGND.
33-
48
CH0 to CH15
Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be
programmed as differential or single-ended.
49
AV_DD1
Positive analog power supply
50
AV_DD2
51
DAC6-OUT
52
DAC7-OUT Output of DAC channels 6, 7, and 8
53
DAC8-OUT
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