AMC7812 Datasheet, PDF (49/92 Pages) Texas Instruments – 12-Bit ANALOG MONITORING AND CONTROL SOLUTION with Multichannel ADC, DACs, and Temperature Sensors

AMC7812
www.ti.com
SBAS513D – JANUARY 2011 – REVISED OCTOBER 2012
POWER SUPPLY SEQUENCE
The preferred (not required) order for applying power is IOVDD, DVDD/AVDD and then AVCC. All registers
initialize to the default values after these supplies have been established. Communication with the AMC7812 will
be valid after a 250µS maximum power-on reset delay. The default state of all analog blocks is off as determined
by the power-down register (6Bh). Before writing to this register, a hardware reset should be issued to ensure
specified operation of the AMC7812. Communication to the AMC7812 will be valid after a maximum 250µS reset
delay from the rising edge of RESET.
If DVDD falls below 2.7V, the minimum supply value of DVDD, either a hardware or power-on reset should be
issued before proper operation can be resumed.
To avoid activating the ESD protection diodes of the AMC7812, GPIO-4, GPIO-5, GPIO-6 and GPIO-7 inputs
should not be applied before the AVDD is established. Also, if using the external reference configuration of the
ADC, ADC-REF-IN/CMP should not be applied before AVDD.
PRIMARY COMMUNICATION INTERFACE
The AMC7812 communicates with the system controller through the primary communication interface, which can
be configured as either an I²C-compatible two-wire bus or an SPI bus. When the SPI/I2C pin is tied to ground,
the I²C interface is enabled, and the SPI is disabled. When the SPI/I2C pin is tied to IOVDD, the I²C interface is
disabled, and SPI is enabled.
I²C-Compatible Interface
This device uses a two-wire serial interface compatible with the I²C-bus specification, version 2.1. The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I²C-compatible devices connect to the I²C bus through open-drain I/O pins SDA
and SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the start and stop of data transfers. A slave device receives and/or transmits data on the bus under
control of the master device. The AMC7812 works as a slave and supports the following data transfer modes, as
defined in the I²C-bus specification: standard mode (100kbps), fast mode (400kbps), and high-speed mode
(3.4Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are
referred to as F/S mode in this document. The protocol for high-speed mode is different from the F/S mode, and
is referred to as Hs mode. The AMC7812 supports 7-bit addressing. However 10-bit addressing and general call
addressing are not supported. The slave address of the AMC7812 is determined by the status of pins A0, A1,
and A2, as shown in Table 8.
A0
GND
GND
GND
GND
IOV_DD
IOV_DD
IOV_DD
IOV_DD
Table 8. Slave Addresses
A1
GND
GND
IOV_DD
IOV_DD
GND
GND
IOV_DD
IOV_DD
A2
GND
IOV_DD
GND
IOV_DD
GND
IOV_DD
GND
IOV_DD
SLAVE ADDRESS
1100001
1100010
1100100
1100101
0101100
0101101
0101110
0101111
Copyright © 2011–2012, Texas Instruments Incorporated
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