AMC7812 Datasheet, PDF (72/92 Pages) Texas Instruments – 12-Bit ANALOG MONITORING AND CONTROL SOLUTION with Multichannel ADC, DACs, and Temperature Sensors

AMC7812
SBAS513D – JANUARY 2011 – REVISED OCTOBER 2012
www.ti.com
ADC CHANNEL REGISTER 1 (Read/Write, Address = 51h, Default = 0000h)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0 SE13 SE14 SE15 0
0
BIT 9
0
BIT 8
0
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
These bits specify the external analog auxiliary input channels (CH13, CH14,and CH 15) to be converted. The
specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC Channel Register 0, and then
bit 14 to bit 12 of ADC Channel Register 1. The input is converted when the corresponding bit is set ('1').
Bits[14:12]
SEn: External single-ended analog input CHn. The result is stored in the ADC-n-Data Register in straight binary format.
ADC GAIN REGISTER (Read/Write, Address = 52h, Default = FFFFh)
MSB
BIT
15
ADG0
BIT
14
ADG1
BIT
13
ADG2
BIT
12
ADG3
BIT
11
ADG4
BIT
10
ADG5
BIT 9
ADG6
BIT 8
ADG7
BIT 7
ADG8
BIT 6
ADG9
BIT 5
ADG10
BIT 4
ADG11
BIT 3
ADG12
BIT 2
ADG13
BIT 1
ADG14
LSB
BIT 0
ADG15
Bit 15
Bit 14
Bit 13
Bit 12
Bit[11:0]
ADG0.
When ADG0 = '1', the analog input range of single-ended input CH0 (SE0) is 0 to (2 · V_REF) or differential input pair
DF(CH0+/CH1–) is (–2 · V_REF) to (+2 · V_REF).
When ADG0 = '0', the analog input range of single-ended input CH0 (SE0) is 0 to V_REF or differential input pair
DF(CH0+/CH1–) is –V_REF to +V_REF.
ADG1.
When ADG1 = '1', the analog input range is 0 to (2 · V_REF).
When ADG1 = '0', the analog input range of single-ended input CH1 (SE1) is 0 to V_REF.
ADG2.
When ADG2 = '1', the analog input range of single-ended input CH2 (SE2) is 0 to (2 · V_REF) or differential input pair
DF(CH2+/CH3–) is (–2 · V_REF) to (+2 · V_REF).
When ADG2 = '0', the analog input range of single-ended input CH2 (SE2) is 0 to V_REF or differential input pair
DF(CH2+/CH3–) is –V_REF to +V_REF.
ADG3.
When ADG3 = '1', the analog input range is 0 to (2 · V_REF).
When ADG3 = '0', the analog input range of single-end input CH3 (SE3) is 0 to V_REF.
ADG4 to ADG15.
When these bits = '1', the analog input range is 0 to (2 · V_REF).
When these bits = '0', the analog input range of CHn (where n = 4 to 15) is 0 to V_REF
AUTO-DAC-CLR-SOURCE REGISTER (Read/Write, Address = 53h, Default = 0004h)
This register selects which alarm forces the DAC into a clear state, regardless of which DAC operation mode is
active, auto or manual.
Table 26. AUTO-DAC-CLR-SOURCE Register
BIT
NAME
DEFAULT R/W
DESCRIPTION
15
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14 CH0-ALR-CLR
0
CH0 alarm clear bit.
If CH0-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
R/W the CH0-ALR bit in the Status Register are set ('1'), then DAC-n is forced to a clear status.
If CH0-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear
status.
13 CH1-ALR-CLR
0
CH1 alarm clear bit.
If CH1-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
R/W the CH1-ALR bit in the Status Register are set ('1'), then DACn is forced to a clear status.
If CH1-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear
status.
12 CH2-ALR-CLR
0
CH2 alarm clear bit.
If CH2-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
R/W the CH2-ALR bit in the Status Register are set ('1'), then DACn is forced to a clear status.
If CH2-ALR_CLR = '0', then CH2-ALR goes to '1' and does not force any DAC to a clear
status.
72
Submit Documentation Feedback
Product Folder Links: AMC7812
Copyright © 2011–2012, Texas Instruments Incorporated