TMS320C6748_1 Datasheet, PDF (87/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
LPSC
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Module Name
Table 6-9. PSC1 Default Module Configuration
Power Domain
Default Module State
EDMA3 Channel Controller 1
USB0 (USB2.0)
USB1 (USB1.1)
GPIO
UHPI
EMAC
DDR2 (and SCR_F3)
McASP0 ( + McASP0 FIFO)
SATA
VPIF
SPI 1
I2C 1
UART 1
UART 2
McBSP0 ( + McBSP0 FIFO)
McBSP1 ( + McBSP1 FIFO)
LCDC
eHRPWM0/1
MMCSD1
uPP
ECAP0/1/2
EDMA3 Transfer Controller 2
—
—
SCR_F0 (and bridge F0)
SCR_F1 (and bridge F1)
SCR_F2 (and bridge F2)
SCR_F6 (and bridge F3)
SCR_F7 (and bridge F4)
SCR_F8 (and bridge F5)
Bridge F7 (DDR Controller path)
Shared RAM (including SCR_F4
and bridge F6)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
PD_SHRAM
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Auto Sleep/Wake Only
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
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Peripheral Information and Electrical Specifications
87