TMS320C6748_1 Datasheet, PDF (177/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
Table 6-81. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 052D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
0x01E0 0530
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0532
PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0534
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0536
PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
0x01E0 053A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 053B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
0x01E0 053C
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
0x01E0 053D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0542
PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0546
PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0548
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
0x01E0 054A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 054B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
0x01E0 054C
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
0x01E0 054D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
DMA Registers
0x01E0 1000
DMAREVID
DMA Revision Register
0x01E0 1004
TDFDQ
DMA Teardown Free Descriptor Queue Control Register
0x01E0 1008
DMAEMU
DMA Emulation Control Register
0x01E0 1800
TXGCR[0]
Transmit Channel 0 Global Configuration Register
0x01E0 1808
RXGCR[0]
Receive Channel 0 Global Configuration Register
0x01E0 180C
RXHPCRA[0]
Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810
RXHPCRB[0]
Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820
TXGCR[1]
Transmit Channel 1 Global Configuration Register
0x01E0 1828
RXGCR[1]
Receive Channel 1 Global Configuration Register
0x01E0 182C
RXHPCRA[1]
Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830
RXHPCRB[1]
Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840
TXGCR[2]
Transmit Channel 2 Global Configuration Register
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Peripheral Information and Electrical Specifications 177