TMS320C6748_1 Datasheet, PDF (145/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
Table 6-59. General Timing Requirements for SPI0 Master Modes (continued)
NO.
PARAMETER
Input
Polarity = 0, Phase = 0,
Hold
from SPI0_CLK falling
Time,
SPI0_S
OMI
Polarity = 0, Phase = 1,
from SPI0_CLK rising
8 t_{ih(SPC_SOMI)M} valid
after
Polarity = 1, Phase = 0,
from SPI0_CLK rising
receive
edge of _{Polarity = 1, Phase = 1,}
SPI0_CL _{from SPI0_CLK falling}
K
1.2V
MIN
MAX
4
4
4
4
1.1V
MIN
MAX
4
4
4
4
1.0V
MIN
MAX
5
5
5
5
UNIT
ns
Table 6-60. General Timing Requirements for SPI0 Slave Modes⁽¹⁾
NO.
PARAMETER
9 t_c(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
10 t_w(SPCH)S
Pulse Width High, SPI0_CLK, All Slave Modes
11 t_w(SPCL)S
Pulse Width Low, SPI0_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Setup time, transmit
data written to SPI
12 t_{su(SOMI_SPC)S} before initial clock
edge from
master. ^{(3) (4)}
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
13 t_{d(SPC_SOMI)S}
Delay, subsequent
bits valid on
SPI0_SOMI after
transmit edge of
SPI0_CLK
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Output hold time,
SPI0_SOMI valid
14 t_{oh(SPC_SOMI)S} after
receive edge of
SPI0_CLK
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Input Setup Time,
SPI0_SIMO valid
15 t_{su(SIMO_SPC)S} before
receive edge of
SPI0_CLK
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.2V
MIN
40 ⁽²⁾
MAX
256P
18
18
2P
1.1V
MIN
50 ⁽²⁾
MAX
256P
22
22
2P
1.0V
MIN
60 ⁽²⁾
MAX
256P
27
27
UNIT
ns
ns
ns
2P
2P
2P
2P
ns
2P
2P
2P
2P
2P
2P
17
20
27
17
20
27
ns
17
20
27
17
20
27
0.5S-6
0.5S-16
0.5S-20
0.5S-6
0.5S-16
0.5S-20
ns
0.5S-6
0.5S-16
0.5S-20
0.5S-6
0.5S-16
0.5S-20
1.5
1.5
1.5
1.5
1.5
1.5
ns
1.5
1.5
1.5
1.5
1.5
1.5
(1) P = SYSCLK2 period; S = t_c(SPC)S (SPI slave bit clock period)
(2) This timing is limited by the timing shown or 2P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Peripheral Information and Electrical Specifications 145