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TMS320C6748_1 Datasheet, PDF (216/254 Pages) Texas Instruments – Fixed/Floating-Point DSP
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TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
6.25.2 uPP Electrical Data/Timing
www.ti.com
Table 6-107. Timing Requirements for uPP (see Figure TBD )
1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX
1 tc(INCLK)
Cycle time, CHn_CLK
SDR mode 13.33
20
26.66
ns
DDR mode 26.66
40
53.33
2 tw(INCLKH)
Pulse width, CHn_CLK high
SDR mode
5
8
10
ns
DDR mode
10
16
20
3 tw(INCLKL)
Pulse width, CHn_CLK low
SDR mode
5
8
10
ns
DDR mode
10
16
20
4 tsu(STV-INCLKH) Setup time, CHn_START valid before CHn_CLK high
4
5.5
6.5
ns
5 th(INCLKH-STV) Hold time, CHn_START valid after CHn_CLK high
0.8
0.8
0.8
ns
6 tsu(ENV-INCLKH) Setup time, CHn_ENABLE valid before CHn_CLK high
4
5.5
6.5
ns
7 th(INCLKH-ENV) Hold time, CHn_ENABLE valid after CHn_CLK high
0.8
0.8
0.8
ns
8
tsu(DV-INCLKH)
Setup time, CHn_DATA/XDATA valid before CHn_CLK
high
4
5.5
6.5
ns
9
th(INCLKH-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
0.8
0.8
0.8
ns
10 tsu(DV-INCLKL) Setup time, CHn_DATA/XDATA valid before CHn_CLK low 4
5.5
6.5
ns
11 th(INCLKL-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
0.8
0.8
0.8
ns
19 tsu(WTV-INCLKL) Setup time, CHn_WAIT valid before CHn_CLK high
4
5.5
6.5
ns
20 th(INCLKL-WTV)
21 tc(2xTXCLK)
Hold time, CHn_WAIT valid after CHn_CLK high
Cycle time, 2xTXCLK input clock(1)
0.8
0.8
0.8
ns
6.66
10
13.33
ns
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-108. Switching Characteristics Over Recommended Operating Conditions for uPP
(see Figure TBD)
NO.
PARAMETER
12 tc(OUTCLK)
Cycle time, CHn_CLK
SDR mode
DDR mode
13 tw(OUTCLKH)
Pulse width, CHn_CLK high
SDR mode
DDR mode
14 tw(OUTCLKL)
Pulse width, CHn_CLK low
SDR mode
DDR mode
15 td(OUTCLKH-STV) Delay time, CHn_START valid after CHn_CLK high
16 td(OUTCLKH-ENV) Delay time, CHn_ENABLE valid after CHn_CLK high
17 td(OUTCLKH-DV) Delay time, CHn_DATA/XDATA valid after CHn_CLK high
18 td(OUTCLKL-DV) Delay time, CHn_DATA/XDATA valid after CHn_CLK low
1.2V
MIN MAX
13.33
26.66
5
10
5
10
2
11
2
11
2
11
2
11
1.1V
MIN MAX
20
40
8
16
8
16
2
15
2
15
2
15
2
15
1.0V
MIN MAX
26.66
53.33
10
20
10
20
2
21
2
21
2
21
2
21
UNIT
ns
ns
ns
ns
ns
ns
ns
216 Peripheral Information and Electrical Specifications
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