TMS320C6748_1 Datasheet, PDF (132/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
6.15.2 McBSP Electrical Data/Timing
The following assume testing over recommended operating conditions.
6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
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Table 6-48. Timing Requirements for McBSP0 [1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)
NO.
PARAMETER
2 t_c(CKRX)
3 t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5
t_su(FRH-CKRL)
Setup time, external FSR high before CLKR
low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR int
CLKR ext
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int
CLKR ext
8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
CLKR ext
CLKX int
10
t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
11 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX int
CLKX ext
1.2V
MIN
2P or 20 ⁽²⁾⁽³⁾
P - 1⁽⁴⁾
14
4
6
3
14
4
3
3
14
4
6
3
MAX
1.1V
MIN
2P or 25⁽²⁾⁽³⁾
P - 1⁽⁴⁾
15.5
5
6
3
15.5
5
3
3
15.5
5
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
132 Peripheral Information and Electrical Specifications
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