TMS320C6748_1 Datasheet, PDF (147/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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NO.
17 t_{d(ENA_SPC)M}
18 t_{d(SPC_ENA)M}
TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
Table 6-61. Additional SPI0 Master Timings, 4-Pin Enable Option ^(1)(2)(3)
PARAMETER
Delay from slave assertion of SPI0_ENA active to first
SPI0_CLK from master.⁽⁴⁾
Max delay for slave to deassert SPI0_ENA after final SPI0_CLK
edge to ensure master does not begin the next transfer.⁽⁵⁾
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
1.2V
MIN
MAX
3P+5
1.1V
MIN
MAX
3P+5
1.0V
MIN
MAX
3P+6
UNIT
0.5M+3P+5
3P+5
0.5M+3P+5
3P+5
0.5M+3P+6
ns
3P+6
0.5M+3P+5
0.5M+3P+5
0.5M+3P+6
0.5M+P+5
0.5M+P+5
0.5M+P+6
P+5
0.5M+P+5
P+5
0.5M+P+5
P+6
ns
0.5M+P+6
P+5
P+5
P+6
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-59).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
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Peripheral Information and Electrical Specifications 147