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THS1206 Datasheet, PDF (8/41 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS | |||
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THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTERS
SLAS217D â MAY 1999 â REVISED APRIL 2000
timing specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
td(DATA_AV)
td(o)
tpipe
Delay time
Delay time
Latency
5
ns
5
ns
5
CONV
CLK
timing specification of the single conversion modeâ
PARAMETER
tc
Clock cycle of the internal clock oscillator
tw1
Pulse width, CONVST
tdA
Aperture time
t2
Time between consecutive start of single conversion
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 1
â Timing parameters are ensured by design but are not tested.
TEST CONDITIONS
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
3 analog inputs, TL = 3
4 analog inputs, TL = 4
1 analog input, TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
MIN
159
1.5Ãtc
2Ãtc
3Ãtc
4Ãtc
5Ãtc
TYP MAX
167
175
1
6Ãtc
7Ãtc
8Ãtc
9Ãtc
3Ãt2 +6Ãtc
t2 +7Ãtc
t2 +8Ãtc
t2 +9Ãtc
7Ãt2 +6Ãtc
3Ãt2 +7Ãtc
2Ãt2 +8Ãtc
2Ãt2 +9Ãtc
13Ãt2 +6Ãtc
5Ãt2 +7Ãtc
3Ãt2 +8Ãtc
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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