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THS1206 Datasheet, PDF (10/41 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTERS
SLAS217D – MAY 1999 – REVISED APRIL 2000
sampling rate (continued)
Table 2. Maximum Conversion Rate in Single Conversion Mode
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
3 single-ended channels
4 single-ended channels
1 differential channel
2 differential channels
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
NUMBER OF
CHANNELS
1
2
3
4
1
2
2
3
MAXIMUM CONVERSION
RATE PER CHANNEL
3 MSPS
2 MSPS
1.5 MSPS
1.2 MSPS
3 MSPS
2 MSPS
1.5 MSPS
1.2 MSPS
single conversion mode
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can
be selected to be sampled simultaneously (see Table 2).
t2
CONVST
AIN
Sample N
t1
td(A)
t1
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 1. Timing of Single Conversion Mode
The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n × tc. This
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.
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