THS1206 Datasheet, PDF (25/41 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTERS
SLAS217D – MAY 1999 – REVISED APRIL 2000
timing and signal description of the THS1206 (continued)
write timing (using R/W, CS0-controlled)
Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
tsu(R/W)
ÎÎÎÎÎÎÎÎ ^WR
ÎÎÎÎÎÎ ^th(R/W)
RD
tsu
th
D(0–11)
90%
90%
DATA_AVÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Figure 14. Write Timing Diagram Using R/W (CS0-controlled)
write timing parameter (RD-controlled)
PARAMETER
tsu(R/W)
tsu
th
th(R/W)
tw(CS)
Setup time, R/W stable to last CS valid
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
5
ns
5
ns
5
ns
10
ns
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