CD4051B-Q1 Datasheet, PDF (8/18 Pages) Texas Instruments – CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

CD4051BĆQ1, CD4052BĆQ1, CD4053BĆQ1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC-LEVEL CONVERSION
SCHS354 − AUGUST 2004
electrical specifications
PARAMETER
TEST CONDITIONS
VIS VDD
(V)
(V)
LIMITS AT
INDICATED
TEMPERATURES
25°C
UNIT
MIN TYP MAX
−3-dB cutoff
frequency,
channel ON
(sine-wave input)
Total harmonic
THD _distortion
RL = 1 kΩ,
VOS at COM OUT/IN,
See Note 2,
VOS at COM OUT/IN
VEE = VSS, 20log VOS/VIS = −3 dB,
VOS at any channel
RL = 10 kΩ,
See Note 2
CD4053 5
10
CD4052 5
10
CD4051 5
10
2
5
3
10
5
15
30
25
20
MHz
60
0.3
0.2
%
0.12
VEE = VSS, fis = 1-kHz sine wave
−40-dB
feedthrough
frequency
RL = 1 kΩ,
VOS at COM OUT/IN,
See Note 2
CD4053 5
10
CD4052 5
10
CD4051 5
10
(all channels OFF) ^{VEE = VSS, 20log VOS/VIS = −40 dB,}
VOS at any channel
RL = 1 kΩ, between any two channels, See Note 2
5
10
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections, Measured on common
0.12
8
10
12
MHz
8
3
6
−40-dB signal
crosstalk frequency
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections,
Measured on any channel
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 2, Out pin 14
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 15, Out pin 14
CD4052
CD4053
10
MHz
2.5
6
Address or inhibit
to signal crosstalk
RL = 10 kΩ, See Note 4
VEE = 0 V, VSS = 0 V, tr, tf = 20 ns,
VCC = VDD − VSS (square wave)
10
65
65
mVPEAK
NOTES: 2. Peak-to-peak voltage symmetrical about VDD − VEE
2
4. Both ends of channel
8
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