CD4051B-Q1 Datasheet, PDF (12/18 Pages) Texas Instruments – CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

CD4051BĆQ1, CD4052BĆQ1, CD4053BĆQ1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC-LEVEL CONVERSION
SCHS354 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
VDD
1
16
2
15
3
14 IDD
4
13
5
12
6
11
7
10
8
9
CD4051
1
16
2
15
3
14
IDD
4
13
5
12
6
11
7
10
8 CD40529
CD4052
1
16
2
15
3
14
4
13
IDD
5
12
6
11
7
10
8
9
CD4053
Figure 12. OFF Channel Leakage Current, Any Channel OFF
VDD
VDD
VDD
1
16
2
15
IDD
3
14
4
13
5
12
6
11
7
10
8
9
1
16
2
15
IDD
3
14
4
13
5
12
6
11
7
10
8
9
1
16
2
15
IDD
3
14
4
13
5
12
6
11
7
10
8
9
CD4051
CD4052
CD4053
Figure 13. OFF Channel Leakage Current, All Channels OFF
VDD
Output
1
16
2
15
RL
CL
VDD
3
14
4
13
VEE
5
VEE
6
7
8
12
11
VDD
10
VSS _Clock
9
In
VSS
CD4051 ^VSS
Output
CL
RL
VDD
VEE _VEE
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
VDD
VDD
VSS
VSS
Clock
In
VEE
VSS
VDD
1
16
Output
2
15
3
14
RL
CL
4
13
5
12
VEE
6
11 ^VDD
7
10 ^{VSS Clock}
8
9
In
CD4053 _VSS
Figure 14. Propagation Delay, Address Input to Signal Output
Output
VDD
RL
50 pF
VEE
VDD
VDD
VSS _{Clock VEE}
In _VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
tPHL and tPLH ^VSS
CD4051
Output
VDD
1
16
RL
50 pF
2
15
3
14
VEE 4
13
VDD
5
12
VDD
6
11
VSS _{Clock VEE}
7
10
In
VSS
8
9
tPHL and tPLH ^VSS
CD4052
Output
RL
50 pF
VDD
VSS _Clock
In
VEE
VDD
VEE
VSS
Figure 15. Propagation Delay, Inhibit Input to Signal Output
1
16
VDD
2
15
3
14
4
13
5
12
6
11
7
10
8
9
tPHL and tPLH VSS
CD4053
12
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