CD4051B-Q1 Datasheet, PDF (7/18 Pages) Texas Instruments – CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

CD4051BĆQ1, CD4052BĆQ1, CD4053BĆQ1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC-LEVEL CONVERSION
SCHS354 − AUGUST 2004
electrical characteristics, V_SUPPLY = ±5 V, A_V = 1 V, R_L = 100 Ω, unless otherwise noted
(see Note 2) (continued)
PARAMETER
TEST CONDITIONS
VEE
(V)
VDD
(V)
LIMITS AT INDICATED
TEMPERATURES
−40°C
125°C
25°C
MIN TYP
Control (Address or Inhibit), VC
VIL Input low voltage
VIL = VDD through 1kΩ,
VIH = VDD through 1kΩ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VIH Input high voltage
IIN Input current
VIL = VDD through 1kΩ,
VIH = VDD through 1kΩ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VIN = 0 V, 18 V
Address-to-signal
tr, tf = 20 ns, CL = 50 pF,
tpd1
OUT (channels ON RL = 10 kΩ, VSS = 0 V,
or OFF) propagation See Figure 10, Figure 11, and
delay
Figure 14
VSS 5
VSS 10
VSS 15
VSS 5
VSS 10
VSS 15
18
0
5
0
10
0
15
−5
5
1.5
3
4
3.5
7
11
±0.1
1.5
3
4
3.5 3.5
7
7
11
11
±1
±10−5
450
160
120
225
0
5
400
Inhibit-to-signal
tpd2
OUT (channel
turning ON)
propagation delay
tr, tf = 20 ns, CL = 50 pF,
RL = 1 kΩ, VSS = 0 V,
See Figure 11
0
10
0
15
−10
5
160
120
200
0
5
200
Inhibit-to-signal
OUT (channel
tpd3 _{turning OFF)}
propagation delay
tr, tf = 20 ns, CL = 50 pF,
RL = 10 kΩ, VSS = 0 V,
See Figure 15
0
10
0
15
−10
5
90
70
130
Input capacitance,
CIN any address or
5
inhibit input
NOTES: 2: Peak-to-peak voltage symmetrical about VDD − VEE
2
3: Determined by minimum feasible leakage measurement for automatic testing
MAX
1.5
3
4
±0.1
720
320
240
450
720
320
240
400
450
210
160
300
7.5
UNIT
V
V
µA
ns
ns
ns
pF
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