CD4051B-Q1 Datasheet, PDF (10/18 Pages) Texas Instruments – CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

CD4051BĆQ1, CD4052BĆQ1, CD4053BĆQ1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC-LEVEL CONVERSION
SCHS354 − AUGUST 2004
TYPICAL CHARACTERISTICS
ON CHARACTERISTICS FOR
1-OF-8 CHANNELS (CD4051B)
6
VDD = 5 V
VSS = 0 V
4 _{VEE = −5 V}
TA = 255C
2
RL = 100 kW, RL = 10 kW
1 kW
500 W
100 W
0
−2
−4
−6
−6
−4
−2
0
2
4
6
Vis − Input Signal Voltage − V
Figure 5
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4052B)
10 ⁵ _{TA = 255C}
Alternating ÒOÓ
and ÒIÓ Pattern
10 ^{4 CL = 50 pF}
VDD = 15 V
10 ³
VDD = 10 V
10 ²
VDD = 5 V
CL = 15 pF
Test Circuit
f
CD4029
VDD ^B/D
AB
100 Ω
1 ^{10 9}
3 CL
5
13
2
12
4 _CD4052 14
15
6
11
7
8
Ι
10
1
10
10 ²
10 ³
10 ⁴
10 ⁵
f − Switching Frequency − kHz
Figure 7
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4051B)
10 ⁵ _{TA = 255C}
Alternating O
Test Circuit
VDD
and I Pattern
10 ^{4 CL = 50 pF}
VDD = 15 V
B/D
f
CD4029
AB C
VDD
100 Ω 11 10 9
13
10 ³
14
15
12 CD4051
1
VDD = 10 V
5
2
3
10 ²
VDD = 5 V
4 _{8 7 6 CL}
100 Ω
Ι
10
1
CL = 15 pF
10
10 ²
10 ³
10 ⁴
10 ⁵
f − Switching Frequency − kHz
Figure 6
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4053B)
10 ⁵ _{TA = 255C}
Alternating O
and I Pattern
10 ^{4 CL = 50 pF}
VDD = 15 V
VDD = 10 V
VDD _f ^{Test Circuit}
10 ³
100 W
9
3
4 CL
12
100 W
5
13
CD4053 ₂
10
1
10 ²
VDD = 5 V
11
15
6
14
7
CL = 15 pF
Ι
8
10
1
10
10 ²
10 ³
10 ⁴
10 ⁵
f − Switching Frequency − kHz
Figure 8
10
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