BQ4010 Datasheet, PDF (8/14 Pages) Texas Instruments – 8Kx8 Nonvolatile SRAM

bq4010/bq4010Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
tPF
VCC slew, 4.75 to 4.25 V
tFS
VCC slew, 4.25 to VSO
tPU
VCC slew, VSO to VPFD (max.)
Min.
300
10
0
tCER
Chip enable recovery time
40
Data-retention time in
tDR
absence of V_CC
10
Data-retention time in
tDR-N
absence of V_CC
6
tWPT
Write-protect time
40
Typ.
-
-
-
80
-
-
100
Max.
-
-
-
120
-
-
150
Unit
µs
µs
µs
ms
Conditions
Time during which SRAM is
write-protected after VCC passes
VPFD on power-up.
years
years
µs
TA = 25°C. (2)
TA = 25°C (2); industrial
temperature range (-N) only.
Delay after VCC slews down past
VPFD before SRAM is write-
protected.
Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
6-8
Sept. 1996 D