BQ4010 Datasheet, PDF (6/14 Pages) Texas Instruments – 8Kx8 Nonvolatile SRAM

bq4010/bq4010Y
Write Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
-70/-70N -85/-85N -150/-150N
-200
Symbol
Parameter
tWC
Write cycle time
Min. Max. Min. Max. Min. Max. Min. Max. _{Units Conditions/Notes}
70 - 85 - 150 - 200 - ns
Chip enable to end
tCW
of write
55 - 75 - 100 - 150 - ns
(1)
Address valid to end
tAW
of write
55 - 75 - 90 - 150 - ns
(1)
Measured from
tAS
Address setup time
0
-
0
-
0
-
0
- ns address valid to
beginning of write. (2)
Measured from
tWP
Write pulse width
55 - 65 - 90 - 130 - ns beginning of write to
end of write. (1)
Measured from WE
tWR1
Write recovery time
(write cycle 1)
5
-
5
-
5
-
5
- ns going high to end of
write cycle. (3)
Measured from CE
tWR2
Write recovery time ₁₅
(write cycle 2)
-
15
-
15
-
15
-
ns going high to end of
write cycle. (3)
Measured from first
tDW
Data valid to end of ₃₀
-
35
-
50
-
70
-
ns low-to-high transition
write
of either CE or WE.
tDH1
Data hold time
(write cycle 1)
Measured from WE
0
-
0
-
0
-
0
- ns going high to end of
write cycle. (4)
tDH2
Data hold time
(write cycle 2)
Measured from CE
10 - 10 -
0
-
0
- ns going high to end of
write cycle. (4)
Write enabled to
tWZ
output in high Z
I/O pins are in output
0
25
0
30
0
50
0
70 ns _{state. (5)}
Output active from
I/O pins are in output
tOW
end of write
5
-
5
-
5
-
5
-
ns _{state. (5)}
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
6-6
Sept. 1996 D