BQ4010 Datasheet, PDF (4/14 Pages) Texas Instruments – 8Kx8 Nonvolatile SRAM

bq4010/bq4010Y
AC Test Conditions
Parameter
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
Test Conditions
0V to 3.0V
5 ns
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tRC
Read cycle time
tAA
Address access time
tACE
Chip enable access time
Output enable to output
tOE
valid
Chip enable to output
tCLZ
in low Z
tOLZ
Output enable to output
in low Z
tCHZ
Chip disable to output
in high Z
tOHZ
Output disable to
output in high Z
Output hold from
tOH
address change
-70/-70N
Min. Max.
70
-
-
70
- 70
-
35
5
-
5
-
0 25
0 25
10
-
-85/-85N -150/-150N
-200
Min. Max. Min. Max. Min. Max.
85
- 150 - 200 -
-
85
- 150 - 200
-
85 - 150 - 200
-
45 - 70 -
90
5
- 10 - 10
-
5
-
5
-
5
-
0 40 0 60 0 70
0 30 0 50 0 70
10
- 10 -
10
-
Unit Conditions
ns
ns Output load A
ns Output load A
ns Output load A
ns Output load B
ns Output load B
ns Output load B
ns Output load B
ns Output load A
6-4
Sept. 1996 D