TMS320C6454_15 Datasheet, PDF (79/233 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
www.ti.com
SPRS311I – APRIL 2006 – REVISED MARCH 2012
5 C64x+ Megamodule
The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data
memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller, power-
down controller, and external memory controller. The C64x+ Megamodule also provides support for
memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to
the C64x+ Megamodule). Figure 5-1 shows a block diagram of the C64x+ Megamodule.
L1P cache/SRAM
256
L2
256
cache/
SRAM
Internal ²⁵⁶
ROM^(A)
To Chip ³²
registers
128
To primary
switch fabric ₁₂₈
L2 memory
controller
Cache
control
Bandwidth
management
Memory
protection
128
External memory
controller
Configuration
Registers
Slave DMA
Master DMA
L1 program memory controller
256
Cache control
Bandwidth management
Memory protection
Advanced event
triggering
(AET)
256
256
IDMA
256
C64x+ CPU
Instruction fetch
SPLOOP buffer
16/32−bit instruction dispatch
Instruction decode
Data path 1
Data path 2
M1
L1 S1 xx D1
xx
M2
D2 xx S2 L2
xx
A register file
B register file
256
64
L1 data memory controller
Cache control
256
Bandwidth management
Memory protection
64
Interrupt
and exception
controller
Power control
32
L1D cache/SRAM
A. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Figure 5-1. 64x+ Megamodule Block Diagram
For more detailed information on the TMS320C64x+ Megamodule on the C6454 device, see the
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
5.1 Memory Architecture
The TMS320C6454 device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory
(L1P), and a 32KB level-1 data memory (L1D).
The L1P memory configuration for the C6454 device is as follows:
• Region 0 size is 0K bytes (disabled).
• Region 1 size is 32K bytes with no wait states.
The L1D memory configuration for the C6454 device is as follows:
• Region 0 size is 0K bytes (disabled).
• Region 1 size is 32K bytes with no wait states.
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C64x+ Megamodule
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