TMS320C6454_15 Datasheet, PDF (157/233 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
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SPRS311I – APRIL 2006 – REVISED MARCH 2012
Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module^{(1) (2) (3)}
(see Figure 7-32)
NO.
PARAMETER
-720
-850
A-1000/-1000
UNIT
MIN
MAX
1
t_c(EKO)
2
t_w(EKOH)
3
t_w(EKOL)
4
t_t(EKO)
5
t_d(EKIH-EKOH)
6
t_d(EKIL-EKOL)
Cycle time, AECLKOUT
Pulse duration, AECLKOUT high
Pulse duration, AECLKOUT low
Transition time, AECLKOUT
Delay time, AECLKIN high to AECLKOUT high
Delay time, AECLKIN low to AECLKOUT low
E - 0.7
EH - 0.7
EL - 0.7
1
1
E + 0.7 ns
EH + 0.7 ns
EL + 0.7 ns
1 ns
8 ns
8 ns
(1) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(2) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN
AECLKOUT1
1
5
6
3
2
4
4
Figure 7-32. AECLKOUT Timing for the EMIFA Module
7.10.3.1 Asynchronous Memory Timing
Table 7-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module^{(1) (2) (3)}
(see Figure 7-33 and Figure 7-34)
-720
-850
NO.
A-1000/-1000
UNIT
MIN MAX
3
t_{su(EDV-A OEH)}
4
t_h(AOEH-EDV)
5
t_{su(ARDY-EKOH)}
6
t_h(EKOH-ARDY)
7
t_{w(ARDY )}
8
t_d(ARDY-HOLD)
Setup time, AEDx valid before AAOE high
Hold time, AEDx valid after AAOE high
Setup time, AARDY valid before AECLKOUT low
Hold time, AARDY valid after AECLKOUT low
Pulse width, AARDY assertion and deassertion
Delay time, from AARDY sampled deasserted on AECLKOUT falling to
beginning of programmed hold period
6.5
ns
0
ns
1
ns
2
ns
2E + 5
ns
4E
ns
9
t_{su(ARDY-HOLD)}
Setup time, before end of programmed strobe period by which AARDY
should be asserted in order to insert extended strobe wait states.
2E
ns
(1) E = AECLKOUT period in ns for EMIFA
(2) To ensure data setup time, simply program the strobe width wide enough.
(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to ensure setup and hold time is met.
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C64x+ Peripheral Information and Electrical Specifications 157
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