TMS320C6454_15 Datasheet, PDF (133/233 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
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SPRS311I – APRIL 2006 – REVISED MARCH 2012
7.7.3.2 PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20. The PLLM
register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits
(RATIO) in the PLL controller pre-divider register (PREDIV).
31
16
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
5
4
0
PLLM
R/W-0h
Figure 7-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Bit Field
31:5 Reserved
4:0 PLLM
Table 7-20. PLL Multiplier Control Register (PLLM) Field Descriptions
Value
0
0h
Eh
13h
18h
1Dh
1Fh
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with
the PLL divider ratio bits (RATIO) in PREDIV.
x1 multiplier rate
x15 multiplier rate
x20 multiplier rate
x25 multiplier rate
x30 multiplier rate
x32 multiplier rate
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C64x+ Peripheral Information and Electrical Specifications 133
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