TMS320C6454_15 Datasheet, PDF (156/233 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
SPRS311I – APRIL 2006 – REVISED MARCH 2012
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7.10.3 EMIFA Electrical Data/Timing
Table 7-42. Timing Requirements for AECLKIN for EMIFA^{(1) (2)}
(see Figure 7-31)
-720
-850
NO.
A-1000/-1000
UNIT
1
t_c(EKI)
2
t_w(EKIH)
3
t_w(EKIL)
4
t_t(EKI)
5
t_J(EKI)
Cycle time, AECLKIN
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
Period Jitter, AECLKIN
MIN
MAX
6 ⁽³⁾
40 ns
2.7
ns
2.7
ns
2 ns
0.02E⁽⁴⁾ ns
(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
(2) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
(4) This timing only applies when AECLKIN is used for EMIFA.
5
1
4
2
AECLKIN
3
4
Figure 7-31. AECLKIN Timing for EMIFA
156 C64x+ Peripheral Information and Electrical Specifications
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