TMS320C6454_15 Datasheet, PDF (185/233 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6454
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SPRS311I – APRIL 2006 – REVISED MARCH 2012
Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP^{(1) (2)}
(see Figure 7-52)
NO.
PARAMETER
-720
-850
A-1000/-1000
UNIT
MIN
MAX
1
t_{d(CKSH-CKRXH)}
2
t_c(CKRX)
3
t_w(CKRX)
4
t_d(CKRH-FRV)
9
t_d(CKXH-FXV)
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input⁽³⁾
Cycle time, CLKR/X
CLKR/X int
Pulse duration, CLKR/X high or CLKR/X low CLKR/X int
Delay time, CLKR high to internal FSR valid CLKR int
CLKX int
Delay time, CLKX high to internal FSX valid
CLKX ext
1.4
6P or 10 ^{(4) (5) (6)}
C - 1 ⁽⁷⁾
-2.1
-1.7
1.7
10 ns
ns
C + 1⁽⁷⁾ ns
3.3 ns
3
ns
9
12
t_{dis(CKXH-DXHZ)}
13
t_d(CKXH-DXV)
14
t_d(FXH-DXV)
Disable time, DX high impedance following
last data bit from CLKX high
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
-3.9
4
ns
2.1
9
-3.9 + D1⁽⁸⁾
2.1 + D1⁽⁸⁾
4 + D2⁽⁸⁾
9 + D2⁽⁸⁾
ns
-2.3 + D1⁽⁹⁾ 5.6 + D2⁽⁹⁾
1.9 + D1⁽⁹⁾
9 + D2⁽⁹⁾
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(5) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(6) Use whichever value is greater.
(7) C = H or L
S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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C64x+ Peripheral Information and Electrical Specifications 185
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