AMC7812SPAPR Datasheet, PDF (75/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812
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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013
HW-DAC-CLR-EN 1 REGISTER (Read/Write, Address = 57h, Default = 0000h)
This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.
MSB
BIT
15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT
BIT 3 2
0
H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR
11
10
9
8
7
6
5
4
3
2
1
0
0
LSB
BIT BIT
10
00
Bits[14:3]
H1CLRn: Hardware clear DAC-n enable 1 bit.
If H1CLRn = '1', DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low.
If H1CLRn = '0', pulling the DAC-CLR-1 pin low does not effect the state of DAC-n.
DAC CONFIGURATION REGISTER (Read/Write, Address = 58h, Default = 0000h)
MSB
BIT 15
0
BIT 14
0
BIT 13 BIT 12 BIT 11
0
0
SLDA
11
BIT 10
SLDA
10
BIT 9
SLDA
9
BIT 8
SLDA
8
BIT 7
SLDA
7
BIT 6
SLDA
6
BIT 5
SLDA
5
BIT 4
SLDA
4
BIT 3
SLDA
3
BIT 2
SLDA
2
BIT 1
SLDA
1
LSB
BIT 0
SLDA
0
Bits[11:0]
SLDA-n: DAC synchronous load enable bit.
If SLDA-n = '1', synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n Latch is loaded
with the value of the corresponding DACn-Data Register, and the output of DAC-n is updated immediately. The internal
load DAC signal ILDAC is generated by writing a '1' to the ILDAC bit in the AMC Configuration Register. In synchronous
Load, a write command to the DAC-n-Data Register updates that register only, and does not change the DAC-n output.
If SLDA-n = '0', asynchronous load is enabled. A write command to the DAC-n-Data Register immediately updates the
DAC-n Latch and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default
value of SLDA-n = '0'. The AMC7812 updates the DAC Latch only if the ILDAC bit was set ('1'), thereby eliminating
unnecessary glitch. Any DAC channels that have not been accessed are not reloaded. When the DAC Latch is updated,
the corresponding output changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n
Mode bits do not equal '00'). In auto mode, the DAC Latch is always updated asynchronously.
NOTE
The DACs can be forced into a clear state immediately by the external DAC-CLR-n signal,
by alarm events, and by writing to the SW-DAC-CLR Register. In these cases, the SLDA-n
bit is ignored.
DAC GAIN REGISTER (Read/Write, Address = 59h, Default = 0000h)
The DACn GAIN bits specify the output range of DACn.
MSB
BIT 15 BIT 14 BIT 13 BIT 12
0
0
0
0
BIT 11
DAC11
GAIN
BIT 10
DAC10
GAIN
BIT 9
DAC9
GAIN
BIT 8
DAC8
GAIN
BIT 7
DAC7
GAIN
BIT 6
DAC6
GAIN
BIT 5
DAC5
GAIN
BIT 4
DAC4
GAIN
BIT 3
DAC3
GAIN
BIT 2
DAC2
GAIN
BIT 1
DAC1
GAIN
LSB
BIT 0
DAC0
GAIN
Bits[11:0]
DACnGAIN: DACn gain bit.
If DACn GAIN = '1', the gain = 5 and the output is 0 to 5 · VREF
If DACn GAIN = '0', the gain = 2 and the output is 0 to 2 · VREF
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