AMC7812SPAPR Datasheet, PDF (11/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812
www.ti.com
SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013
SDA
t_{SU, STA}
SCL
Sr
t_FDA
t_RDA
t_{HD, DAT}
t_{HD, STA}
t_{SU, DAT}
t_RCL1(1)
t_HIGH
t_FCL
t_LOW
t_RCL
t_LOW
t_HIGH
Sr P
t_{SU, STO}
t_RCL1(1)
= Current Source Pull-Up
= Resistor Pull-Up
Sr = Repeated START Condition
P = STOP Condition
(1) First rising edge of the SCL signal after Sr and after each acknowledge bit.
Figure 2. Timing for High-Speed (Hs) Mode Devices on the I²C Bus
TIMING CHARACTERISTICS: SDA and SCL for Hs Mode⁽¹⁾
At –40°C to +105°C, AV_DD = 4.5V to 5.5V, DV_DD = 2.7V to 5.5V, AGND = DGND = 0V, and IOV_DD = 2.7V to 5.5V, unless
otherwise noted.
f_SCL ⁽²⁾
t_{SU, STA}
t_{HD, STA}
t_LOW
t_HIGH
t_{SU, DAT}
t_{HD, DAT}
t_RCL
t_RCL1
PARAMETER
SCL clock frequency
Setup time for (repeated) start condition
Hold time (repeated) start condition
Low period of the SCL clock
High period of the SCL clock
Data setup time
Data hold time
Rise time of SCL signal
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit
C_B = 10pF to 100pF
MIN
MAX
0
3.4
160
—
160
—
160
—
60
—
10
—
0
70
10
40
10
80
C_B = 400pF
MIN
0
160
160
320
120
10
0
20
MAX
1.7
—
—
—
—
—
150
80
20
160
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
t_FCL
t_RDA
t_FDA
t_{SU, STO}
C_B ⁽³⁾
t_SP
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Set-up time for stop condition
Capacitive load for SDA and SCL lines
Pulse width of spike suppressed
10
40
20
80 ns
10
80
20
160 ns
10
80
20
160 ns
160
—
160
— ns
10
100
—
400 pF
0
10
0
10 ns
(1) All values refer to V_IHmin and V_ILmax levels.
(2) An SCL operating frequency of at least 1kHz is recommended to avoid activating the I²C timeout function. See the Timeout Function
section for details.
(3) For bus line loads where C_B is between 100pF and 400pF, the timing parameters must be linearly interpolated.
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