TL16C552AFNR Datasheet, PDF (7/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
recommended operating conditions
Supply voltage, VDD
Clock high-level input voltage, VIH(CLK)
Clock low-level input voltage, VIL(CLK)
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency, fclock
Operating free-air temperature, TA
I suffix
M suffix
MIN NOM MAX UNIT
4.75
5 5.25 V
2
VDD V
0
0.8 V
2
VDD V
0
0.8 V
16 MHz
– 40
85
°C
– 55
125
package thermal characteristics
PARAMETER
TEST CONDITIONS
R_θJA
R_θJC
TJ
Junction-to-ambient thermal impedance
Junction-to-case thermal impedance
Junction temperature
Board mounted, no air flow
FN Package
MIN TYP MAX
52
14
115
HV Package
MIN TYP MAX
74
3
150
UNIT
°C/W
°C/W
°C/W
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
VOH High-level output voltage
VOL Low-level output voltage
II
Input current
IOH = – 12 mA for PD0 – PD7,
IOH = – 4 mA for all other outputs (see Note 2),
IOL = 12 mA for PD0 – PD7,
IOL = 12 mA for INIT, AFD, STB, and SLIN,
IOL = 4 mA for all other outputs
VDD = 5.25 V (see Note 3),
All other terminals are floating
2.4
V
0.4 V
± 10 µA
II(CLK) Clock input current
VI = 0 to 5.25 V
± 10 µA
IOZ
High-impedance output current
VDD = 5.25 V,
VO = 0 with chip deselected or
VO = 5.25 V with chip and write mode selected (see Note 2)
± 20 µA
IDD
Supply current
VDD = 5.25 V,
Inputs at 0.8 V or 2 V,
No loads on outputs,
fclock = 8 MHz
50 mA
NOTES: 2. Excluding INIT, AFD, STB, and SLIN. They are open-drain terminals with an internal pullup resistor to VDD of approximately 10 KΩ.
3. Excluding the TRI input terminal. It contains an internal pulldown resistor of approximately 5 kΩ.
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
tw1
Pulse duration, CLK ↑ (external clock) (see Figure 1)
tw2
Pulse duration, CLK ↓ (external clock) (see Figure 1)
tw3
Pulse duration, RESET
MIN
31
31
1000
MAX
UNIT
ns
ns
ns
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